Upgrading firmware LOM and SB in SUN E2900

Been a while since my last posting in this blog :D Now, I'm gonna show you how to upgrade firmware LOM and SB in SUN E2900. Even though these server no longer available to get the new one (end-of-life); here, in my project, there are lots of E2900 to be maintained. The user requested for an upgrade on the firmware ILOM due to the compatibility issue.

First, we need to check on the existing version

lom>showboards -p v

Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.3 Build_03
/N0/IB6 Yes 5.20.3 Build_03
/N0/SB0 Yes 5.20.13 Build_01
/N0/SB2 Yes 5.20.3 Build_03
/N0/SB4 Yes 5.20.6 Build_02

lom>showsc -v

SC: SSC1
System Controller V2

SC date: Fri Jan 15 02:16:00 PST 2008
PST GMT-08:00 Pacific Standard Time
SC uptime: 6 minutes 26 seconds

ScApp version: 5.20.3 Build_03
Version build: 3.0
Version String: 5.20.3
RTOS version: 46

SC POST diag level: max

Clock source is: 75MHz

Solaris Host Status: Powered Off

Chassis HostID: 845xxxxx
PROC RTUs installed: 0
PROC Headroom Quantity: 0
lom>


lom>showboards -p version -v

Component Segment Compatible In Date Time Build Version
--------- ------- ---------- -- ---- ---- ----- -------
SSC1/FP0 - - - - - - RTOS version: 46
SSC1/FP1 ScApp Reference 12 10/21/2006 06:38 3.0 5.20.3
SSC1/FP1 Ver - - 10/21/2006 06:38 3.0 5.20.3 Build_03
/N0/IB6/FP0 iPOST Yes 12 10/21/2006 06:36 3.0 5.20.3
/N0/IB6/FP0 Ver - - 10/21/2006 06:38 3.0 5.20.3 Build_03
/N0/IB6/FP0 Info - 12 10/21/2006 06:38 3.0 5.20.3
/N0/SB0/FP0 POST Yes 12 06/04/2009 02:44 1.0 5.20.13
/N0/SB0/FP0 OBP Yes 12 06/04/2009 02:43 1.0 5.20.13
/N0/SB0/FP0 Ver - - 06/04/2009 02:46 1.0 5.20.13 Build_01
/N0/SB0/FP0 Info - 12 06/04/2009 02:46 1.0 5.20.13
/N0/SB0/FP1 POST Yes 12 06/04/2009 02:44 1.0 5.20.13
/N0/SB0/FP1 OBP Yes 12 06/04/2009 02:43 1.0 5.20.13
/N0/SB0/FP1 Ver - - 06/04/2009 02:46 1.0 5.20.13 Build_01
/N0/SB0/FP1 Info - 12 06/04/2009 02:46 1.0 5.20.13
/N0/SB2/FP0 POST Yes 12 10/21/2006 06:25 3.0 5.20.3
/N0/SB2/FP0 OBP Yes 12 10/21/2006 06:21 3.0 5.20.3
/N0/SB2/FP0 Ver - - 10/21/2006 06:29 3.0 5.20.3 Build_03
/N0/SB2/FP0 Info - 12 10/21/2006 06:29 3.0 5.20.3
/N0/SB2/FP1 POST Yes 12 10/21/2006 06:25 3.0 5.20.3
/N0/SB2/FP1 OBP Yes 12 10/21/2006 06:21 3.0 5.20.3
/N0/SB2/FP1 Ver - - 10/21/2006 06:29 3.0 5.20.3 Build_03
/N0/SB2/FP1 Info - 12 10/21/2006 06:29 3.0 5.20.3
/N0/SB4/FP0 POST Yes 12 05/23/2007 08:56 2.0 5.20.6
/N0/SB4/FP0 OBP Yes 12 05/23/2007 08:54 2.0 5.20.6
/N0/SB4/FP0 Ver - - 05/23/2007 08:57 2.0 5.20.6 Build_02
/N0/SB4/FP0 Info - 12 05/23/2007 08:57 2.0 5.20.6
/N0/SB4/FP1 POST Yes 12 05/23/2007 08:56 2.0 5.20.6
/N0/SB4/FP1 OBP Yes 12 05/23/2007 08:54 2.0 5.20.6
/N0/SB4/FP1 Ver - - 05/23/2007 08:57 2.0 5.20.6 Build_02
/N0/SB4/FP1 Info - 12 05/23/2007 08:57 2.0 5.20.6

Based on the info, we can see that the SB0 have version 5.20.13, SB2 have version 5.20.3 and SB4 have 5.20.6 firmware version. RTOS has firmware version 5.20.3 as well. In this case, i'm upgrading all the version to 5.20.14.

1. Download Patch 114527-15

2. Save the file on an internal server (the server that is still a network with the server firmware to be upgraded.

3. flashupdate -f ftp://root:root_password@ip_address_ftp_server///tmp/114527-15/114527-15 scapp rtos

As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.
Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.

Do you want to continue? [no] yes

Waiting for critical processes to finish. This may take a while.
Critical processes have finished.
No boards can be updated.

Rebooting the SC to automatically complete the upgrade.

Rebooting. All network client connections closed. Reestablish any needed connections.



Software Reset...


@(#) SYSTEM CONTROLLER(SC) POST 46 2006/09/26 07:52
PSR = 0x044010e5
PCR = 0x04004000

Memory size = 128MB

SelfTest running at DiagLevel:0x20

SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2

COM4 port _ Intr #2

System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002229
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14

Port0 interrupt generation Tests INTR #14

SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read

Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.0 Degree(C)

Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.50 Degree(C)

Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 29.50 Degree(C)

Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up



Flashupdate
Verifying network connectivity to 192.168.12.101... Passed.
Connecting to 192.168.12.101...
Transferring sgrtos.flash via FTP : 2048 Transferring sgrtos.flash via FTP : 4608
-------- truncated -------

Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 0/11 = 100%
ok

Connecting to 192.168.12.101...
Transferring sgsc.flash via FTP : 2048 Transferring sgsc.flash via FTP : 4608
------------truncated file ------------
Transferring sgsc.flash via FTP : 6553876
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 0/101 = 0%
----------- truncated -----------
Updating flashprom sectors at address 0x36000000: 101/101 = 100%
ok



Software Reset...


@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000

Memory size = 128MB

SelfTest running at DiagLevel:0x20

SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2

COM4 port _ Intr #2

System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002229
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14

Port0 interrupt generation Tests INTR #14

SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read

Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.50 Degree(C)

Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.0 Degree(C)

Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 30.0 Degree(C)

Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up


Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.

Sun Fire System Firmware
RTOS version: 49
ScApp version: 5.20.14 Build_02
SC POST diag level: min

Enter Password:
Connected.
lom>

4. Verify output
lom>showsc
SC: SSC1
System Controller V2

SC date: Fri Jan 14 02:33:10 PST 2008
SC uptime: 3 minutes 22 seconds

ScApp version: 5.20.14 Build_02
RTOS version: 49

Solaris Host Status: Powered Off

Chassis HostID: 845xxxx
PROC RTUs installed: 0
PROC Headroom Quantity: 0
lom>showboards -p v

Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.14 Build_02
/N0/IB6 Yes 5.20.3 Build_03
/N0/SB0 Yes 5.20.13 Build_01
/N0/SB2 Yes 5.20.3 Build_03
/N0/SB4 Yes 5.20.6 Build_02

5. Upgrade Component SB and IB
lom>flashupdate -f ftp://root:root_password@ip_address_ftp_server///tmp/114527-15/114527-15 all rtos

As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.

After this update you must reboot each active domain that was upgraded.

Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.
Do you want to continue? [no] y
Waiting for critical processes to finish. This may take a while.
Critical processes have finished.

Retrieving: flashupdate -f ftp://root:root_password@ip_address_ftp_server///tmp/114527-15/114527-15/lw8cpu.flash
Validating ................... Done

Programming PROM /N0/SB0/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Programming PROM /N0/SB0/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Programming PROM /N0/SB2/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Programming PROM /N0/SB2/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Programming PROM /N0/SB4/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Programming PROM /N0/SB4/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done

Retrieving: flashupdate -f ftp://root:root_password@ip_address_ftp_server///tmp/114527-15/114527-15/lw8pci.flash
Validating ........ Done

Programming PROM /N0/IB6/FP0
Erasing ....... Done
Programming ....... Done
Verifying ....... Done

Rebooting the SC to automatically complete the upgrade.

Rebooting. All network client connections closed. Reestablish any needed connections.
Fri Jan 15 02:40:15 app1lom lom: Stopping all services on this SC
Fri Jan 15 02:40:15 app1lom lom: All services on this SC have been stopped.


Software Reset...


@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000

Memory size = 128MB

SelfTest running at DiagLevel:0x20

SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2

COM4 port _ Intr #2

System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002228
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14

Port0 interrupt generation Tests INTR #14

SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read

Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 25.0 Degree(C)

Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.50 Degree(C)

Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 31.50 Degree(C)

Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up


Flashupdate
Verifying network connectivity to 192.168.12.101... Passed.
Connecting to 192.168.12.101...
Transferring sgrtos.flash via FTP : 2048
---- Truncated -----
Transferring sgrtos.flash via FTP : 696120
Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 0/11 = 0%Updating flashprom sectors at address 0x20000000: 11/11 = 100%
ok

Connecting to 192.168.12.101...
Transferring sgsc.flash via FTP : 2048
------------truncated --------------
Transferring sgsc.flash via FTP : 6553876
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 0/101 = 0%Updating flashprom sectors at address 0x36000000: 9/101 = 8%Updating flashprom sectors at address 0x36000000: 40/101 = 39%Updating flashprom sectors at address 0x36000000: 65/101 = 64%Updating flashprom sectors at address 0x36000000: 89/101 = 88%Updating flashprom sectors at address 0x36000000: 101/101 = 100%
ok



Software Reset...


@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000

Memory size = 128MB

SelfTest running at DiagLevel:0x20

SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2

COM4 port _ Intr #2

System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002228
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14

Port0 interrupt generation Tests INTR #14

SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read

Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 25.0 Degree(C)

Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.0 Degree(C)

Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 31.50 Degree(C)

Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up


Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.

Sun Fire System Firmware
RTOS version: 49
ScApp version: 5.20.14 Build_02
SC POST diag level: min

Enter Password:
Connected.

lom>

6. Verify output
lom>showboards -p v

Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.14 Build_02
/N0/IB6 Yes 5.20.14 Build_02
/N0/SB0 Yes 5.20.14 Build_02
/N0/SB2 Yes 5.20.14 Build_02
/N0/SB4 Yes 5.20.14 Build_02

Read more... »»

The History of SPARC Processor

When we talk about Sun Microsystem’s hardware, SPARC will always be the first that come directly into our mind. Indeed, SPARC (Scalable Processor ARChitecture) has been Sun Microsystem’s flagship processor architecture for over note years.
With Sun’s dedication to innovation and flexibility, the processor had gone through many revisions over the years in an endeavor to stay on the cutting edge. Eighty-eight of the 500 super-computers in the world used SPARC by June 2002.

In 1985, the SPARC microprocessor instruction set architecture was originally designed, but quickly underwent a 32-bit revision in 1986 (SPARC Version 7) They first designed for use in Sun-4 workstation and server systems, replacing the Motorola 68000 family. SPARC processors apace gained in popularity, and were utilized in SMP servers built by, among others, Sun, Solbourne, and Fujitsu.
Even though the processor was designed for and used in SunOS (Solaris), SPARC processor can be used with other operating systems, such as FreeBSD,OpenBSD,NetBSD and Linux. In attempt to increase processing speed as much as possible, The SPARC instruction set was designed to be minimalist, with as few feature as possible (including the inability to multiply or divide)
The SPARC processor was also designed to be scalable by allowing all types of processor from tiny dedicated processors to huge server-level ones to use the same core instruction set. The first example of SPARC processor contained 128 general-purpose registers-eight global, 32 available to software, and 24 for a run window to transfer duty call parameters and return values.
The SPARC Version 8 (V8), the enhancement architecture, was released in 1990. Adding 16 highly flexible double-precision registers instead of the previous 32. Its instruction set regained the multiply and divide. Every double-precision register, could be utilized as either two single-precision registers (for a total of 32 single-precision registers) or, by using an odd-even pair of double precisions-registers, be utilized as a quad-precision run (resulting in 8 sib precision registers
In 1993, SPARC Version 9 (56-bit data and addressing), also known as SPARC64, was released. Adding sixteen more double-precision registers that could be combined and used as eight quad-precision registers. But could not be used a 32 single-precision registers.
In third-quarter of 2005, Sun Microsystem released the UltraSPARC T1 source code to an open-source project called OpenSPARC. Nowadays, three fully open source versions of the SPARC architecture exists. LEON, a 32-bit, single thread SPARC V8 version, OpenSPARC T1, a 64-bit, 32-thread version of SPARC V9, and OpenSPARC T2, a 64-bit, 64-thread version of SPARC V9.

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SCSA Certification

Just like linux, Solaris is another “ derivative product” of UNIX. Even though Linux is more popular in UNIX market, having a SCSA (SUN Certified System Administration) certification will make you have a better income and grow professionally.
The SCSA holders are in high demand in larger sectors such as Telecommunication, Financial firms, Oil or even in Military and so on. It means that the will make some money more easily.
This certification, in general, measure the essential system-administration-management skills of Solaris operating system. And it’s also useful for technical application support staff who responsible for administering and maintaining a network server running on the Solaris operating system.

Off course, an IT professionals working as a system administration (sys-admin) in a UNIX environment must have this kind of certification. Solaris 8, 9 and 10 SCSA program are offered by SUN Microsystem. It consists of two parts. And the candidates must have passed both part to acquires claim their certificate
If you have already had the previous version of this certificate, you must upgrade it by taking an upgrade exam.This certificate has their own lifetime. It is only valid for two years from the date of certification.

Even though there are some mandatory requirements, it’s better for you to have at least six months of experience in the field of system administration before taking the first part of the exam. And you’ll need one more year experience before appearing for the second part of the exam.Besides that, you must have a basic understanding, if not a master, of UNIX fundamental and good knowledge of Solaris OE commands before you can take the SCSA certification.
SCSA exam is quite easy, for the person who is well prepared course :D.

Lots of book and study guide you can find nowadays. You can search it here amazon or anywhere else.
Or maybe you want to order some certification package, it’s a comprehensive study-guide made exclusively made for the purpose. Even there are many SCSA workshops available.
Those simulations will not only sharpen your knowledge but also will give you great understanding on the subject so you can get a 100% in the exams.

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A Brief History of Solaris

Solaris, the UNIX-based operating system developed by SUN Microsystem, was born in 1987. AT&T and SUN Microsystem tried to combine the leading Unix versions (BSD, XENIX, and System V) into one operating system.
In 1991, SUN Microsystem replaced it's existing Unix operating system (SunOS 4) with one based on SVR4, called Solaris 2.
Contained with many new advances, including use of the Open Network Computing (ONC) functionality, NIS+ and OpenWindows graphical user interface, Solaris 2 was specially designed for symmetric multiprocessing.

And now, for more than twenty-years, numerous versions of Solaris has been released with great innovations to adapt the changing of the computer environment, trying to anticipate where the computer world is going.
Innovations that Solaris OS has made will takes pages to be described. I’ll show you some of the most important milestones:
1. 1996 – Solaris 2.5.1 – NFSv3 file system and NFS/TCP, CDE (Common Desktop Environment), included support for the Macintosh PowerPC and the CDE (Common Desktop Environment), expanded user and group IDs to 32 bits.
2. 1997 – Solaris 2.6 – Kerberos 5 security encryption, WebNFS file system and large file support to increase Solaris internet performance
3. 1998 – Solaris 2.7 (renamed just Solaris 7) – 64-bit released, dramatically increased its performance, capacity, and scalability. Native support for file system meta-data logging (UFS logging)
4. 2000 – Solaris 8 – first OS to combine datecentre and dot-com requirements, offering support for IPMP, IPv6 and IPSEC, Multipath I/O.
5. 2002 – Solaris 9 – OpenWindows (in favour of Linux compatibility), and added a Resource Manager, the Solaris Volume Manager, extended file attributes, and the iPlanet Directory Server
6. 2005 – Solaris 10 – free of charge, more compatible with Linux and IBM system, Dynamic Tracing (DTrace), NFSv4, Java Desktop System based on GNOME, ZFS (later in 2006)
7. 2006 – OpenSolaris Project – In the first year, the community had grown to 29 user groups globally with over than 14,000 members, working on 31 active projects.
The “evolution” of the Solaris OS shows the capacity of Sun Microsystem to be on the cutting edge of the computing world without losing touch with the current computing environment. New versions of Solaris is regularly released incorporated the latest development in computer technology and also included more cross-platform compatibility and incorporating the advances of other systems.

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UNIX in a nutshell

An operating system (or “OS”) is a set of programs that controls a computer. It controls both the hardware (things you can touch – keyboards, displays and disk drives) and the sotfware (application program that you run, such as a word processor).
Some computers have a single-user OS, which means only one person can use the computer at a time. Many older OSes (like DOS) can also do only one job at a time. But almost any computer can do a lot more if it has a multiuser, multitasking operating system like UNIX. These powerful OSes let many people use the computer at the same time and let each user run several jobs at once.Unix operating systems are widely used in both servers and workstations. The Unix environment and the client-server program model were essential elements in the development of the Internet and the reshaping of computing as centered in networks rather than in individual computers

As mentioned above, Unix was designed to be portable, multi-tasking and multi-user in a time-sharing configuration. Unix systems are characterized by various concepts: the use of plain text for storing data; a hierarchical file system; treating devices and certain types of inter-process communication (IPC) as files; and the use of a large number of software tools, small programs that can be strung together through a command line interpreter using pipes, as opposed to using a single monolithic program that includes all of the same functionality. These concepts are known as the Unix philosophy.

There are many different versions of UNIX . Until few years ago, there were just two main versions: the line of UNIX releases that started at the AT&T, and the other line from the University of California at Berkeley. Some other major commercial versions include SunOS, Solaris, AIX, HP/UX and ULTRIX. Some of the freely available versions include LINUX and FreeBSD.

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